In a power semiconductor device, on-resistance and withstand voltage are in a trade-off relationship and defined by a band gap value of a substrate material. Therefore, for offering greater performance than a device formed by using a silicon (Si) substrate, which has been widely used as a power device, it is an effective way to use a substrate material having a larger band gap than that of silicon. In particular, silicon carbide (SiC) has a sufficiently large band gap about three times as large as that of silicon, and when compared with a case of using a substrate made of gallium nitride (GaN) or the like, a substrate made of silicon carbide has characteristics that semiconductor regions of p type and n type conductivities can be easily formed and oxide films can be formed by thermal oxidation. Therefore, silicon carbide has the possibility of achieving a device such as a high-performance MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and is attracting a lot of attention.
However, an oxide film formed on a SiC substrate has a serious problem. That is, when the SiC substrate is thermally oxidized, carbon (C) remains in an oxide film formed on a surface of the SiC substrate and a high-density interface state is formed in the oxide film. As a result, the channel mobility of MOSFET is greatly deteriorated, and the on-resistance of the device is significantly increased. Furthermore, carbon in an oxide film causes the decrease in reliability of the oxide film, which is the major hindrance to the achievement of the MOSFET using a SiC substrate.
A junction FET (Junction Field Effect Transistor: J-FET) has been known as a device structure capable of avoiding the above-described problem of the oxide film interface. The junction FET is a type of device in which a pn junction is used as a gate to control a channel, and is a normally-on device in which a negative voltage is usually applied to a gate to extend a depletion layer in a channel, thereby turning off the conduction between a source and a drain. From a fail-safe perspective, the use of the normally-on device is limited so as not to decrease the reliability. Therefore, a normally-off type is generally desired in the power device. In the junction FET using a silicon substrate, the increase of the withstand voltage in the normally-off type is difficult, but when a SiC substrate is used, the increase of the withstand voltage in the normally-off type can be achieved by narrowing the channel width. This is because the diffusion potential of the pn junction of SiC is as high as about 2.5 V and the channel can be completely depleted even when a negative voltage is not applied to a gate. By this means, the high-performance normally-off junction FET capable of avoiding the problem of the interface state of an oxide film can be achieved.
For example, Japanese Patent Application Laid-Open Publication No. 2004-134547 (Patent Document 1) is publicly known as a document relating to a normally-off silicon carbide junction FET. The Patent Document 1 discloses a technology for a junction FET or a static induction transistor using a SiC substrate, in which an ion implantation with a relatively low energy is performed when forming a p type gate region, thereby achieving the reduction in on-resistance and improving the blocking effect.
Here, FIG. 17 shows the junction FET shown in FIG. 6 according to the fourth embodiment of the Patent Document 1. The junction FET shown in FIG. 17 is formed on an n+ type substrate to be a drain region, and a drain electrode 6 is formed on a lower surface of the n+ type substrate 1. An n− type drift layer 2 is formed on the n+ type substrate 1, and a plurality of trenches 5 extending in a direction along a main surface of the n+ type substrate 1 are formed and arranged in a stripe shape on an upper surface of the n− type drift layer 2. On the parts of the upper surface of the n− type drift layer 2 on which the trenches 5 are not formed, source regions 23 are formed along the trenches 5 in a stripe shape. More specifically, the n− type drift layer 2 is formed on the n+ type substrate 1, the source regions 23 are formed on the n− type drift layer 2, and the trenches 5 reaching an intermediate depth of the n− type drift layer 2 from upper surfaces of the source regions 23 are formed. A source contact layer 7 is formed in an extending direction of the trench 5 on each upper surface of the adjacent source regions 23 respectively interposing the trench 5 therebetween except on the edge portions of the upper surface of the source region 23 near the trenches 5.
On a surface of the n− type drift layer 2 and a sidewall and a bottom surface of each trench 5, gate regions 24 are formed except the regions on which the source regions 23 are formed. Note that the gate region 24 formed on the sidewall of the trench 5 is in contact with the source region 23 in contact with the sidewall of the same trench 5 on an upper surface of the gate region 24, and a pn junction region corresponding to an interface between the gate region 24 and the source region 23 is exposed from a semiconductor substrate 21 on the sidewall of the trench 5.